Modern integrated circuits include a very large amount of logic circuits such as flip-flops, logic gates and the like. These circuits are tested in various manners, in order to provide an indication about the functionality of the integrated circuit.
Integrated circuit designers are force to use relatively limited resources (such as dedicated test pins, silicone footprint) in order to perform complex tests.
One common method for checking an integrated circuit involves connecting multiple scan logic circuits in a serial manner, such as to form a very long scan chain. A typical scan logic circuit can operate in a functional mode and in scan mode. In scan mode scan data propagates along the scan chain, from one scan logic circuit to another scan logic circuit. In functional mode data propagates between logic circuits in paths that differ from the scan data paths.
Signals, such as clock signals and data signals propagate differently during scan mode and functional mode, as they travel through different paths. A clock signal can be skewed and even dramatically skewed in one mode while being substantially un-skewed in the other operational mode.
Clock skews can cause timing violations such as setup or hold violations. These violations can cause scan data to be corrupted and even force a scan logic circuit to enter un unknown logical state.
FIG. 1 illustrates a portion 10 of a prior art scan chain. Portion 10 includes two flip-flops 20 and 30, two multiplexers (denoted MUX) 40 and 50, and two boxes 60 and 70 that represent combinational logic that form a part of the functional path. The latter are various logic circuits that are connected to flip flop 20 and 30 during functional mode.
Each multiplexer has a data input, a scan data input and a control input that receives a S/F mode signal indicating whether the portion 10 operates in scan mode or functional mode. In response multiplexer 40 and 50 provide data or scan data to the input of the flip flops 20 and 30.
Flip flop 20 receives a first clock signal CLK1 81 while flip flop 30 receives a second clock signal CLK2 82.
Flip flop 20 includes an input transfer gate 22, an input latch 24, an intermediate transfer gate 26 and an output latch 28. Flip flop 30 includes an input transfer gate 32, an input latch 34, an intermediate transfer gate 36 and an output latch 38. Input transfer gate 22 is opened when CLK1 81 is low and output transfer gate 28 is opened when clock signal CLK1 81 is high. Input transfer gate 32 is opened when CLK2 82 is low and output transfer gate 38 is opened when clock signal CLK2 82 is high.
In order to ensure proper operation of flip flops 20 and 30 the output signal from flip flop 20 must be steady for a set up period before the rising edge of CLK2 82 and be steady for a hold period after the rising edge of CLK2.
The output signal of flip flop 20 is steady after the falling edge of CLK1 81 and can also be steady in response to the behavior of the signal provided to it from the input latch 24.
If there is a negligible time difference between CLK1 81 and CLK2 82 the timing conditions can be maintained. On the other hand, if there is a substantial skew between CLK1 and CLK 2 the timing conditions are not maintained. A race occurs when the timing differences result in timing violations, and especially when a certain scan flip flop samples irrelevant information.
Various techniques were applied in order to reduce these timing violation. A first technique provides a delay circuit in the scan mode path. The delay period of the delay circuit resembles a delay introduced by the functional mode path. U.S. patent application publication number 2004/0015759 of Chen et al., which is incorporated herein by reference provides such a solution. Another technique extended the time period required to change a state of a scan logic circuit by providing a weak scan output signal driver. U.S. Pat. No. 6,389,566 of Wagner et al., which is incorporated herein by reference, provides such a solution. Yet a further technique involves simulating the performance of the scan chain and re-designing the connectivity between scan logic circuits until proper scan chain performance is achieved.
There is a need to provide an efficient method for race prevention, and a device that has race prevention capabilities, especially in scan chains.